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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2002 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com CS4362 114 db, 192 khz 6-channel d/a converter features 24-bit conversion up to 192 khz sample rates 114 db dynamic range -100 db thd+n supports pcm or dsd data formats selectable digital filters volume control with soft ramp ?1dbstepsize ? zero crossing click-free transitions dedicated dsd inputs low clock jitter sensitivity simultaneous support for two synchronous sample rates for dvd audio c or stand-alone operation description the CS4362 is a complete 6-channel digital-to-analog system including digital interpolation, fifth-order delta- sigma digital-to-analog conversion, digital de-emphasis, volume control and analog filtering. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. the CS4362 accepts pcm data at sample rates from 4 khz to 192 khz, dsd audio data, and operates over a wide power supply range. these features are ideal for multi-channel audio systems including dvd players. sacd players, a/v receivers, digital tv?s and vcr?s, mixing consoles, effects processors and set-top box systems. ordering information CS4362-kq -10 to 70 48-pin lqfp CS4362-bq -40 to 85 48-pin lqfp cdb4362 evaluation board i external mute control rst volum e c ontrol interpolation filter analog filter ? dac mixer volum e control ? dac analog filter interpolation filter volum e c ontrol interpolation filter analog filter ? dac mixer volum e control ? dac analog filter interpolation filter volum e c ontrol interpolation filter analog filter ? dac mixer volum e control ? dac analog filter ao utb3- interpolation filter mclk s e rial p o rt m1/scl/cclk m 2/sda/cdin m0/ad0/cs vlc 2 vq filt+ va gnd vd mutec[1:6] m3/dsd_sclk gnd control port/mode select 6 vls lrck sd i n1 sd i n2 sd i n3 2 sclk l rck2 sclk dsdxx 6 ao utb3+ ao uta3- ao uta3+ ao utb2- ao utb2+ ao uta2- ao uta2+ ao utb1- ao utb1+ ao uta1- ao uta1+ 1 1 mar ?02 ds257pp2
CS4362 2 table of contents 1. characteristics and specifications ........................................................................ 4 2. register quick reference .......................................................................................... 14 3. register description .................................................................................................... 15 4. pin description ............................................................................................................... .. 24 5. applications ................................................................................................................. ..... 27 5.1 grounding and power supply decoupling ....................................................................... 27 5.2 oversampling modes ....................................................................................................... 27 5.3 recommended power-up sequence ............................................................................... 27 5.4 analog output and filtering ............................................................................................. 27 5.5 interpolation filter ......................................................................................................... ... 27 5.6 clock source selection .................................................................................................... 28 5.7 using dsd mode ............................................................................................................. 28 6. control port interface .............................................................................................. 28 6.1 enabling the control port ................................................................................................. 28 6.2 format selection ............................................................................................................. .28 6.3 i 2 c format ....................................................................................................................... 2 9 6.3.1 writing in i 2 c format ........................................................................................... 29 6.3.2 reading in i 2 c format ........................................................................................ 29 6.4 spi format ................................................................................................................... .... 29 6.4.1 writing in spi ...................................................................................................... 29 6.5 memory address pointer (map) ...................................................................................... 30 7. parameter definitions.................................................................................................. 38 8. references ................................................................................................................... ..... 38 9. package dimensions ....................................................................................................... 39 list of figures figure 1. serial mode input timing ................................................................................................. 8 figure 2. direct stream digital - serial audio input timing............................................................. 9 figure 3. control port timing - i 2 c format ................................................................................... 10 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts important notice "preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "advan ce" product informa- tion describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warr anty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that informa tion being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including th ose pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus a nd by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other i ntellectual property rights. cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within yo ur organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not extend to other copying such as copying for general distribu tion, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or technologies described in thi s material and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license and/or quota needs to be obta ined from the competent authorities of the chinese government if any of the products or technologies described in this material is subject to the prc foreig n trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage ("critical applications"). cirrus products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer's risk. purchase of i 2 c components of cirrus logic, inc., or one of its sublicensed associated companies conveys a license under the phillips i 2 c patent rights to use those components in a standard i 2 csystem. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be tr ademarks or service marks of their respective owners.
CS4362 3 figure 4. control port timing - spi format................................................................................... 11 figure 5. typical connection diagram control port...................................................................... 12 figure 6. typical connection diagram stand-alone ..................................................................... 13 figure 7. control port timing, i 2 c format .................................................................................... 30 figure 8. control port timing, spi format.................................................................................... 30 figure 9. single speed (fast) stopband rejection ........................................................................ 31 figure 10. single speed (fast) transition band ............................................................................ 31 figure 11. single speed (fast) transition band (detail) ................................................................ 31 figure 12. single speed (fast) passband ripple .......................................................................... 31 figure 13. single speed (slow) stopband rejection..................................................................... 31 figure 14. single speed (slow) transition band........................................................................... 31 figure 15. single speed (slow) transition band (detail)............................................................... 32 figure 16. single speed (slow) passband ripple......................................................................... 32 figure 17. double speed (fast) stopband rejection..................................................................... 32 figure 18. double speed (fast) transition band........................................................................... 32 figure 19. double speed (fast) transition band (detail)............................................................... 32 figure 20. double speed (fast) passband ripple......................................................................... 32 figure 21. double speed (slow) stopband rejection ................................................................... 33 figure 22. double speed (slow) transition band ......................................................................... 33 figure 23. double speed (slow) transition band (detail) ............................................................. 33 figure 24. double speed (slow) passband ripple ....................................................................... 33 figure 25. quad speed (fast) stopband rejection ....................................................................... 33 figure 26. quad speed (fast) transition band ............................................................................. 33 figure 27. quad speed (fast) transition band (detail) ................................................................. 34 figure 28. quad speed (fast) passband ripple ........................................................................... 34 figure 29. quad speed (slow) stopband rejection...................................................................... 34 figure 30. quad speed (slow) transition band ............................................................................ 34 figure 31. quad speed (slow) transition band (detail) ................................................................ 34 figure 32. quad speed (slow) passband ripple .......................................................................... 34 figure 33. format 0 - left justified up to 24-bit data.................................................................... 35 figure 34. format 1 - i 2 s up to 24-bit data................................................................................... 35 figure 35. format 2 - right justified 16-bit data .......................................................................... 35 figure 36. format 3 - right justified 24-bit data .......................................................................... 35 figure 37. format 4 - right justified 20-bit data .......................................................................... 36 figure 38. format 5 - right justified 18-bit data .......................................................................... 36 figure 39. de-emphasis curve..................................................................................................... 3 6 figure 40. channel pair routing diagram (x = channel pair 1, 2, or 3) ....................................... 36 figure 41. atapi block diagram (x = channel pair 1, 2, or 3) ...................................................... 37 figure 42. recommended output filter........................................................................................ 37 list of tables table 1. digital interface formats - pcm mode............................................................................ 16 table 2. digital interface formats - dsd mode ............................................................................ 16 table 3. atapi decode ............................................................................................................. ... 21 table 4. example digital volume settings .................................................................................... 22 table 5. common clock frequencies........................................................................................... 26 table 6. digital interface format, stand-alone mode options...................................................... 26 table 7. mode selection, stand-alone mode options .................................................................. 26 table 8. direct stream digital (dsd), stand-alone mode options ............................................... 26
CS4362 4 1. characteristics and specifications analog characteristics (full-scale output sine wave, 997 hz; measurement bandwidth 10 hz to 20 khz, unless otherwise specified; test load r l =3k ? ,c l = 100 pf , va = 5 v, vd = 3.3v (see figure 5) for single speed mode fs = 48 khz, sclk = 3.072 mhz, mclk = 12.288 mhz; for double speed mode fs = 96 khz, sclk = 6.144 mhz, mclk = 12.288 mhz; for quad speed mode fs = 192 khz, sclk = 12.288 mhz, mclk = 24.576 mhz; for direct stream digital mode fs = 128 x 48 khz, dsd_sclk = 6.144 mhz, mclk = 12.288 mhz). notes: 1. CS4362-kq parts are tested at 25 c. 2. one-half lsb of triangular pdf dither is added to data. 3. performance limited by 16-bit quantization noise. 4. CS4362-bq parts are tested at the extremes of the specified temperature range and min/max performance numbers are guaranteed across the specified temperature range, t a . typical numbers are takenat25c. parameters symbol min typ max unit CS4362-kq dynamic performance - all pcm modes and dsd (note 1) specified temperature range t a -10 - 70 c dynamic range (note 2) 24-bit unweighted a-weighted 16-bit unweighted (note 3) a-weighted 105 108 - - 111 114 94 97 - - - - db db db db total harmonic distortion + noise (note 2) 24-bit 0 db -20 db -60 db 16-bit 0 db (note 3) -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -94 - - - - - db db db db db db idle channel noise / signal-to-noise ratio - 114 - db interchannel isolation (1 khz) - 90 - db CS4362-bq dynamic performance - all pcm modes and dsd (note 4) specified temperature range t a -40 - 85 c dynamic range (note 2) 24-bit unweighted a-weighted 16-bit unweighted (note 3) a-weighted 102 105 - - 111 114 94 97 - - - - db db db db total harmonic distortion + noise (note 2) 24-bit 0 db -20 db -60 db 16-bit 0 db (note 3) -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -91 - - - - - db db db db db db idle channel noise / signal-to-noise ratio - 114 - db interchannel isolation (1 khz) - 90 - db
CS4362 5 analog characteristics (continued) power and thermal characteristics notes: 5. v fs is tested under load r l and includes attenuation due to z out 6. current consumption increases with increasing fs within a given speed mode and is signal dependant. max values are based on highest fs and highest mclk. 7. i lc measured with no external loading on the sda pin. 8. this specification is violated when the vlc supply is greater than vd and when pin 16 (m1/sda) is tied or pulled low. logic tied to pin 16 needs to be able to sink this current. 9. power down mode is defined as rst pin = low with all clock and data lines held static. 10. valid with the recommended capacitor values on filt+ and vq as shown in figures 5 and 6. parameters symbol min typ max units analog output - all pcm modes and dsd full scale differential output voltage (note 5) v fs 88% v a 92% v a 94% v a vpp quiescent voltage v q -50%v a -vdc max current from v q i qmax -1 - a interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c output impedance (note 5) z out - 100 - ? ac-load resistance r l 3- -k ? load capacitance c l - - 100 pf parameters symbol min typ max units power supplies power supply current normal operation, v a =5v (note 6) v d =5v v d =3.3v interface current, vlc=5v (note 7, 8) vls=5v power-down state (all supplies) (note 9) i a i d i d i lc i ls i pd - - - - - - 50 38 25 2 84 200 55 60 40 - - - ma ma ma a a a power dissipation (note 6) va = 5 v, vd = 3.3 v normal operation power-down (note 9) va = 5 v, vd = 5 v normal operation power-down (note 9) - - - - 335 1 440 1 410 - 575 - mw mw mw mw package thermal resistance ja jc - - 48 15 - - c/watt c/watt power supply rejection ratio (note 10) (1 khz) (60 hz) psrr - - 60 40 - - db db
CS4362 6 analog filter response notes: 11. slow roll-off interpolation filter is only available in control port mode. 12. filter response is not tested but is guaranteed by design. 13. response is clock dependent and will scale with fs. note that the response plots (figures 9 to 32) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 14. single and double speed mode measurement bandwidth is from stopband to 3 fs. quad speed mode measurement bandwidth is from stopband to 1.34 fs. 15. de-emphasis is available only in single speed mode; only 44.1khz de-emphasis is available in stand- alone mode parameter fast roll-off slow roll-off (note 11) unit min typ max min typ max combined digital and on-chip analog filter response - single speed mode (note 12) passband (note 13) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 -0.01 - +0.01 db stopband .547 - - .583 - - fs stopband attenuation (note 14) 90 - - 64 - - db group delay - 12/fs - - 6.5/fs - s passband group delay deviation 0 - 20 khz - - 0.41/fs - 0.14/fs s de-emphasis error (note 15) fs = 32 khz (relative to 1khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 - - - - - - 0.23 0.14 0.09 db db db combined digital and on-chip analog filter response - double speed mode - 96khz (note 12) passband (note 13) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 0 0 - - .296 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 -0.01 - 0.01 db stopband .583 - - .792 - - fs stopband attenuation (note 14) 80 - - 70 - - db group delay - 4.6/fs - - 3.9/fs - s passband group delay deviation 0 - 20 khz - - 0.03/fs - 0.01/fs s combined digital and on-chip analog filter response - quad speed mode - 192khz (note 12) passband (note 13) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 0 0 - - .104 .481 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 -0.01 - 0.01 db stopband .635 - - .868 - - fs stopband attenuation (note 14) 90 - - 75 - - db group delay - 4.7/fs - - 4.2/fs - s passband group delay deviation 0 - 20 khz - - 0.01/fs - 0.01/fs s combined digital and on-chip analog filter response - dsd mode (note 12) passband (note 13) to -0.1 db corner to -3 db corner - - - - - - 0 0 - - 20 120 khz khz frequency response 10 hz to 20 khz - - - -.01 - 0.1 db
CS4362 7 digital characteristics (for kq t a =-10to+70c;forbqt a =-40to+85c;vlc=vls= 1.8 v to 5.5 v) absolute maximum ratings (gnd = 0v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (gnd = 0v; all voltages with respect to ground.) parameters symbol min typ max units high-level input voltage serial data port control port v ih v ih 70% vls 70% vlc - - - - v v low-level input voltage serial data port control port v il v il - - - - 20% vls 20% vlc v v input leakage current (note 8) i in --10 a input capacitance - 8 - pf maximum mutec drive current - 3 - ma mutec high-level output voltage v oh -va-v mutec low-level output voltage v ol -0-v parameters symbol min max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 v v v v input current, any pin except supplies i in -10ma digital input voltage serial data port interface control port interface v ind-s v ind-c -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc 4.5 3.0 1.8 1.8 5.0 3.3 5.0 5.0 5.5 5.5 5.5 5.5 v v v v
CS4362 8 switching characteristics (for kq t a =-10to+70c;forbqt a =-40to+85c;vls= 1.8 v to 5.5 v; inputs: logic 0 = gnd, logic 1 = vls, c l = 30pf) notes: 16. see table 5 on page 26 for suggested mclk frequencies 17. this serial clock is available only in control port mode when the mclk divide bit is enabled. 18. the higher frequency lrck must be an exact integer multiple (1, 2, or 4) of the lower frequency lrck . parameters symbol min typ max units mclk frequency (note 16) single speed mode 1.024 - 51.2 mhz double speed mode 6.400 - 51.2 mhz quad speed mode 6.400 - 51.2 mhz mclk duty cycle 40 50 60 % input sample rate single speed mode double speed mode quad speed mode fs fs fs 4 50 100 - - - 50 100 200 khz khz khz lrck duty cycle 45 50 55 % sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk period t sclkw --ns (note 17) t sclkw --ns sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdata valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdata hold time t sdh 20 - - ns lrck1 to lrck2 frequency ratio (note 18) 0.25 1.00 4.00 2 mclk ----------------- - 4 mclk ----------------- - sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 1. serial mode input timing
CS4362 9 dsd - switching characteristics (t a = -10 to 70 c; logic 0 = gnd; vls = 1.8 v to 5.5 v; logic 1 = vls volts; c l =30pf) note: 19. min is 4 times 64x dsd or 2 times 128x dsd, and max is 12 times 64x dsd or 6 times 128x dsd. the proper mclk to dsd_sclk ratio must be set either by the dif registers or the m0:2 pins parameter symbol min typ max unit master clock frequency (note 19) 4.096 - 38.4 mhz mclk duty cycle (all dsd modes) 40 50 60 % dsd_sclk pulse width low t sclkl 20 --ns dsd_sclk pulse width high t sclkh 20 --ns dsd_sclk frequency (64x oversampled) (128x oversampled) 1.024 2.048 - - 3.2 6.4 mhz mhz dsd_l / _r valid to dsd_sclk rising setup time t sdlrs 20 --ns dsd_sclk rising to dsd_l or dsd_r hold time t sdh 20 --ns sclkh t sclkl t dsd_l, dsd_r dsd_sclk sdlrs t sdh t figure 2. direct stream digital - serial audio input timing
CS4362 10 switching characteristics - control port - i 2 cformat (for kq t a =-10to+70 c; for bq t a =-40to+85 c; vlc = 1.8 v to 5.5 v; inputs: logic 0 = gnd, logic 1=vlc,c l =30pf) notes: 20. data must be held for sufficient time to bridge the transition time, t fc ,ofscl. 21. the acknowledge delay is based on mclk and can limit the maximum transaction speed. 22. for single-speed mode, for double-speed mode, for quad-speed mode. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 20) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc ,t rc -1s fall time scl and sda t fc ,t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling (note 21) t ack -(note22)ns 15 256 fs -------------------- - 15 128 fs -------------------- - 15 64 fs ----------------- - t buf t hdst t low t hdd t high t sud stop s ta rt sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 3. control port timing - i 2 cformat
CS4362 11 switching characteristics - control port - spi format (for kq t a =-10to+70 c; for bq t a =-40to+85 c; vlc = 1.8 v to 5.5 v; inputs: logic 0 = gnd, logic 1=vlc,c l =30pf) notes: 23. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 24. data must be held for sufficient time to bridge the transition time of cclk. 25. for f sck <1mhz. parameter symbol min max unit cclk clock frequency f sclk -mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 23) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl -ns cclk high time t sch -ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 24) t dh 15 - ns rise time of cclk and cdin (note 25) t r2 - 100 ns fall time of cclk and cdin (note 25) t f2 - 100 ns mclk 2 ----------------- - 1 mclk ----------------- - 1 mclk ----------------- - t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 4. control port timing - spi format
CS4362 12 digital audio source vls CS4362 mclk vd aouta1+ 10 8 32 0.1 f + 1f +3.3 v to +5 v sdin1 9 1f 0.1 f + + 20 21 filt+ cmout 7 6 lrck1 sclk1 sdin3 sdin2 39 40 0.1 f 47 f va 0.1 f + 1f 0.1 f +1.8vto+5v +5 v 4 43 lrck2 sclk2 13 analog conditioning and muting aouta1- aoutb1+ 38 37 analog conditioning and muting aoutb1- aouta2+ 35 36 analog conditioning and muting aouta2- aoutb2+ 34 33 analog conditioning and muting aoutb2- aouta3+ 29 30 analog conditioning and muting aouta3- aoutb3+ 28 27 analog conditioning and muting aoutb3- mutec1 41 26 mute drive mutec2 11 12 pcm 31 gnd gnd 5 micro- controller vlc 0.1 f +1.8 v to +5 v 18 dsd audio source 2 48 dsdb2 3 42 dsd_sclk dsda1 dsdb3 dsda3 dsdb1 dsda2 46 47 1 16 15 scl/cclk sda/cdin ado/cs rst 19 17 2k ? 2k ? note*: necessary for i 2 c control port operation note* mutec3 25 24 mutec4 mutec5 23 22 mutec6 figure 5. typical connection diagram control port
CS4362 13 digital audio source vls CS4362 mclk vd aouta1+ 10 8 32 0.1 f + 1f +3.3vto+5v sdin1 9 1f 0.1 f + + 20 21 filt+ cmout 7 6 lrck1 sclk1 sdin3 sdin2 39 40 0.1 f 47 f va 0.1 f + 1f 0.1 f +1.8vto+5v +5 v 4 43 lrck2 sclk2 13 aouta1- aoutb1+ 38 37 aoutb1- aouta2+ 35 36 aouta2- aoutb2+ 34 33 aoutb2- aouta3+ 29 30 aouta3- aoutb3+ 28 27 analog conditioning and muting aoutb3- 11 12 pcm 31 gnd gnd 5 vlc 0.1 f +1.8vto+5v 18 dsd audio source 2 48 dsdb2 3 42 m3(dsd_sclk) dsda1 dsdb3 dsda3 dsdb1 dsda2 46 47 1 16 15 m2 m1 m0 rst 19 17 47 k ? vls note dsd note dsd note dsd : for dsd operation: 1)lrck1mustbetiedtovlsand rem ain static high. 2) m3 pcm stand-alone configuration pin becomes dsd_sclk 22 mutec6 analog conditioning and muting 23 mutec5 analog conditioning and muting 24 mutec4 analog conditioning and muting 25 mutec3 analog conditioning and muting 26 mutec2 analog conditioning and muting 41 mutec1 stand-alone mode configuration 47 k ? note vlc note vlc :ifseriesresistorsare used they must be <1k ohm. if possible tie vlc to the vd supply to reduce possible excess current consumption from vlc. figure 6. typical connection diagram stand-alone
CS4362 14 2. register quick reference addr function 7 6 5 4 3 2 1 0 01h mode control 1 cpen freeze mclkdiv reserved dac3_dis dac2_dis dac1_dis pdn default 00 0 0000 1 02h mode control 2 reserved dif2 dif1 dif0 reserved sdin3clk sdin2clk sdin1clk default 0000000 0 03h mode control 3 szc1 szc0 snglvol rmp_up mutec+/- amute mutec1 mutec0 default 1000010 0 04h filter control reserved reserved reserved filt_sel reserved dem1 dem0 rmp_dn default 0000000 0 05h invert control reserved reserved inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 default 0000000 0 06h mixing control pair 1 (aoutx1) p1_a=b p1atapi4 p1atapi3 p1atapi2 p1atapi1 p1atapi0 p1fm1 p1fm0 default 0010010 0 07h vol. control a1 a1_mute a1_vol6 a1_vol5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 default 0000000 0 08h vol. control b1 b1_mute b1_vol6 b1_vol5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 default 0000000 0 09h mixing control pair 2 (aoutx2) p2_a=b p2atapi4 p2atapi3 p2atapi2 p2atapi1 p2atapi0 p2fm1 p2fm0 default 0010010 0 0ah vol. control a2 a2_mute a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 default 0000000 0 0bh vol. control b2 b2_mute b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 default 0000000 0 0ch mixing control pair 3 (aoutx3) p3_a=b p3atapi4 p3atapi3 p3atapi2 p3atapi1 p3atapi0 p3fm1 p3fm0 default 0010010 0 0dh vol. control a3 a3_mute a3_vol6 a3_vol5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 default 0000000 0 0eh vol. control b3 b3_mute b3_vol6 b3_vol5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 default 0000000 0 12h chip revision part3 part2 part1 part0 reserved reserved reserved reserved default 1110--- -
CS4362 15 3. register description note: all registers are read/write in i 2 c mode and write only in spi, unless otherwise noted. 3.1 mode control 1 (address 01h) 3.1.1 control port enable (cpen) default = 0 0 - disabled 1-enabled function : this bit defaults to 0, allowing the device to power-up in stand-alone mode. the control port mode can be accessed by setting this bit to 1. this will allow the operation of the device to be controlled by the registers and the pin definitions will conform to control port mode. to accomplish a clean power- up, the user should write this bit within 10 ms following the release of reset. 3.1.2 freeze controls (freeze) default = 0 0 - disabled 1-enabled function: this function allows modifications to be made to the registers without the changes taking effect until the freeze is disabled. to make multiple changes in the control port registers take effect simulta- neously, enable the freeze bit, make all register changes, then disable the freeze bit. 3.1.3 master clock divide enable (mclkdiv) default = 0 0 - disabled 1-enabled function: the mclkdiv bit enables a circuit which divides the externally applied mclk signal by 2 prior to all other internal circuitry. 3.1.4 dac pair disable (dacx_dis) default = 0 0-enabled 1 - disabled function: when enabled the respective dac channel pair x (aoutax and aoutbx) will remain in a reset state. it is advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility of audible artifacts. 76543210 cpen freeze mclkdiv reserved dac3_dis dac2_dis dac1_dis pdn 00 0 00001
CS4362 16 3.1.5 power down (pdn) default = 1 0 - disabled 1-enabled function: the entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. the power-down bit defaults to ? enabled ? on power-up and must be disabled before normal operation in control port mode can occur. 3.2 mode control 2 (address 02h) 3.2.1 digital interface format (dif) default = 000 - format 0 ( left justified, up to 24-bit data ) function: these bits select the interface format for the serial audio input. the functional mode bits determine whether pcm or dsd mode is selected. pcm mode: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 33-38. dsd mode: the relationship between the oversampling ratio of the dsd audio data and the required master clock to dsd data rate is defined by the digital interface format pins. 76543210 reserved dif2 dif1 dif0 reserved sdin3clk sdin2clk sdin1clk 00000000 dif2 dif1 dif0 description format figure 000 left justified, up to 24-bit data 033 001 i 2 s, up to 24-bit data 134 010 right justified, 16-bit data 235 011 right justified, 24-bit data 336 100 right justified, 20-bit data 437 101 right justified, 18-bit data 538 110 reserved 111 reserved table1.digitalinterfaceformats-pcmmode dif2 dif1 difo description 0 0 0 64x oversampled dsd data with a 4x mclk to dsd data rate 0 0 1 64x oversampled dsd data with a 6x mclk to dsd data rate 0 1 0 64x oversampled dsd data with a 8x mclk to dsd data rate 0 1 1 64x oversampled dsd data with a 12x mclk to dsd data rate 1 0 0 128x oversampled dsd data with a 2x mclk to dsd data rate 1 0 1 128x oversampled dsd data with a 3x mclk to dsd data rate 1 1 0 128x oversampled dsd data with a 4x mclk to dsd data rate 1 1 1 128x oversampled dsd data with a 6x mclk to dsd data rate table 2. digital interface formats - dsd mode
CS4362 17 3.2.2 serial audio data clock source (sdinxclk) default = 0 0 - sdinx clocked by sclk1 and lrck1 1 - sdinx clocked by sclk2 and lrck2 function: the sdinxclk bit specifies which sclk/lrck input pair is used to clock in the data on the given sdinx line. for more details see ? clock source selection ? on page 28. 3.3 mode control 3 (address 03h) 3.3.1 soft ramp and zero cross control (szc) default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is selected all level changes will take effect immediately in one step. zero cross zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently mon- itored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. soft ramp on zero crossing soft ramp and zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implemented on a signal zero crossing. the 1/8 db level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 76543210 szc1 szc0 snglvol rmp_up reserved amute mutec1 mutec0 10000100
CS4362 18 3.3.2 single volume control (snglvol) default = 0 0 - disabled 1-enabled function: the individual channel volume levels are independently controlled by their respective volume control bytes when this function is disabled. the volume on all channels is determined by the a1 channel volume control byte, and the other volume control bytes are ignored when this function is enabled. 3.3.3 soft volume ramp-up after error (rmp_up) default = 0 0 - disabled 1-enabled function: an un-mute will be performed after executing a filter mode change, after a lrck/mclk ratio change or error, and after changing the functional mode. when this feature is enabled, this un-mute is ef- fected, similar to attenuation changes, by the soft and zero cross bits in the mode control 3 register. when disabled, an immediate un-mute is performed in these instances. note: for best results, it is recommended that this feature be used in conjunction with the rmp_dn bit. 3.3.4 mutec polarity (mutec+/-) default = 0 0-activehigh 1-activelow function: the active polarity of the mutec pin(s) is determined by this register. when set to 0 (default) the mutec pins are high when active. when set to 1 the mutec pin(s) are low when active. note: when the on board mute circuitry is designed for active low, the mutec outputs will be high (un-muted) for the period of time during reset and before this bit is enabled to 1. 3.3.5 auto-mute (amute) default = 1 0 - disabled 1-enabled function: the digital-to-analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-static data will release the mute. detection and muting is done independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mute period. the muting function is affected, similar to volume control changes, by the soft and zero cross bits in the mode control 3 register.
CS4362 19 3.3.6 mute pin control(mutec1, mutec0) default = 00 00 - six mute control signals 01 - three mute control signals 10 - one mute control signal 11 - reserved function: selects how the internal mute control signals are routed to the mutec1 through mutec6 pins. when set to ? 00 ? , there is one mute control signal for each channel: aout1a on mutec1, aout1b on mutec2, etc. when set to ? 01 ? , there are three mute control signals, one for each stereo pair: aout1a and aout1b on mutec1, aout2a and aout2b on mutec2, and aout3a and aout3b on mutec3. when set to ? 10 ? , there is a single mute control signal on the mutec1 pin. 3.4 filter control (address 04h) 3.4.1 interpolation filter select (filt_sel) default = 0 0-fastroll-off 1 - slow roll-off function : this function allows the user to select whether the interpolation filter has a fast or slow roll off. for filter characteristics please see section 1. 3.4.2 de-emphasis control (dem) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates. (see figure 39) de-emphasis is only available in single speed mode. 76543210 reserved reserved reserved filt_sel reserved dem1 dem0 rmp_dn 00000000
CS4362 20 3.4.3 soft ramp-down before filter mode change (rmp_dn) default = 0 0 - disabled 1-enabled function: a mute will be performed prior to executing a filter mode change. when this feature is enabled, this mute is effected, similar to attenuation changes, by the soft and zero cross bits in the mode control 3 register. when disabled, an immediate mute is performed prior to executing a filter mode change. note: for best results, it is recommended that this feature be used in conjunction with the rmp_up bit. 3.5 invert control (address 05h) 3.5.1 invert signal polarity (inv_xx) default = 0 0 - disabled 1-enabled function: when enabled, these bits will invert the signal polarity of their respective channels. 3.6 mixing control pair 1 (channels a1 & b1)(address 06h) mixing control pair 2 (channels a2 & b2)(address 09h) mixing control pair 3 (channels a3 & b3)(address 0ch) 3.6.1 channel a volume = channel b volume (a=b) default = 0 0 - disabled 1-enabled function: the aoutax and aoutbx volume levels are independently controlled by the a and the b channel volume control bytes when this function is disabled. the volume on both aoutax and aoutbx are determined by the a channel attenuation and volume control bytes (per a-b pair), and the b chan- nel bytes are ignored when this function is enabled. 76543210 reserved reserved inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 00000000 76543210 px_a=b pxatapi4 pxatapi3 pxatapi2 pxatapi1 pxatapi0 pxfm1 pxfm0 00100100
CS4362 21 3.6.2 atapi channel mixing and muting (atapi) default = 01001 - aoutax=al, aoutbx=br (stereo) function: the CS4362 implements the channel mixing functions of the atapi cd-rom specification. the atapi functions are applied per a-b pair. refer to table 3 and figure 41 for additional information. atapi4 atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 0 1 1 1 1 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 1 0 0 1 1 mute [(al+br)/2] 10100 ar mute 10101 ar br 10110 ar bl 1 0 1 1 1 ar [(bl+ar)/2] 11000 al mute 11001 al br 11010 al bl 1 1 0 1 1 al [(al+br)/2] 1 1 1 0 0 [(al+br)/2] mute 1 1 1 0 1 [(al+br)/2] br 1 1 1 1 0 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] table 3. atapi decode
CS4362 22 3.6.3 functional mode (fm) default = 00 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) 11 - direct stream digital mode function: selects the required range of input sample rates or dsd mode. when dsd mode is selected for any channel pair then all pairs will switch to dsd mode. 3.7 volume control (addresses 07h, 08h, 0ah, 0bh, 0dh, 0eh) 3.7.1 mute (mute) default = 0 0 - disabled 1-enabled function: the digital-to-analog converter output will mute when enabled. the quiescent voltage on the output will be retained. the muting function is effected, similar to attenuation changes, by the soft and zero cross bits. the mute pins will go active during the mute period according to the mutec bits. 3.7.2 volume control (xx_vol) default = 0 (no attenuation) function: the digital volume control registers allow independent control of the signal levels in 1 db increments from 0 to -127 db. volume settings are decoded as shown in table 4. the volume changes are imple- mented as dictated by the soft and zero cross bits. all volume settings less than -127 db are equivalent to enabling the mute bit. 76543210 xx_mute xx_vol6 xx_vol5 xx_vol4 xx_vol3 xx_vol2 xx_vol1 xx_vol0 00000000 binary code decimal value volume setting 0000000 0 0 db 0010100 20 -20 db 0101000 40 -40 db 0111100 60 -60 db 1011010 90 -90 db table 4. example digital volume settings
CS4362 23 3.8 chip revision (address 12h) 3.8.1 part number id (part) [read only] 1110 - CS4362 function: this read-only register can be used to identify the model number of the device. 76543210 part3 part2 part1 part0 reserved reserved reserved reserved 1110 - - - -
CS4362 24 4. pin description pin name # pin description vd 4 digital power ( input ) - positive power supply for the digital section. refer to the recom- mended operating conditions for appropriate voltages. gnd 5 31 ground ( input ) - ground reference. should be connected to analog ground. mclk 6 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. table 5 illustrates several standard audio sample rates and the required master clock frequencies. lrck1 lrck2 7 10 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. the frequency of the left/right clock must be at the audio sample rate, fs. sdin1 sdin2 sdin3 8 11 13 serial data input ( input ) - input for two ? s complement serial audio data. sclk1 sclk2 9 12 serial clock ( input ) - serial clocks for the serial audio interface. tst 14 44 45 test - these pins need to be tied to analog ground. rst 19 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. va 32 analog power ( input ) - positive power supply for the analog section. refer to the recom- mended operating conditions for appropriate voltages. vls 43 serial audio interface power ( input ) - determines the required signal level for the serial audio interface. refer to the recommended operating conditions for appropriate voltages. vlc 18 control port power ( input ) - determines the required signal level for the control port and stand alone configuration pins. refer to the recommended operating conditions for appropriate volt- ages. sdin3 gnd aoutb2- aouta3+ aoutb3- aoutb2+ va aouta3- aoutb3+ mutec2 mutec3 6 2 4 8 10 1 3 5 7 9 11 1 2 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 mclk dsdb1 vd sdin1 lrck2 dsda2 dsda1 gnd sclk1 sdin2 sclk2 lrck1(dsd_en) m3(dsd_sclk) dsdb3 dsda3 tst CS4362 tst vls tst m2(scl/cclk) m1(sda/cdin) vlc rst filt+ vq mutec6 mutec5 mutec4 m0(ad0/cs) aouta2+ aouta2- aoutb1+ aoutb1- aouta1- aouta1+ dsdb2 mutec1
CS4362 25 vq 21 quiescent voltage ( output ) - filter connection for internal quiescent voltage. vq must be capacitively coupled to analog ground, as shown in the typical connection diagram. the nom- inal voltage level is specified in the analog characteristics and specifications section. vq pre- sents an appreciable source impedance and any current drawn from this pin will alter device performance. however, vq can be used to bias the analog circuitry assuming there is no ac signal component and the dc current is less then the maximum specified in the analog charac- teristics and specifications section. filt+ 20 positive voltage reference ( output ) - positive reference voltage for the internal sampling cir- cuits. requires the capacitive decoupling to analog ground as shown in the typical connection diagram. aouta1 +,- aoutb1 +,- aouta2 +,- aoutb2 +,- aouta3 +,- aoutb3 +,- 39,40 37,38 35,36 33,34 29,30 27,28 differential analog output ( output ) - the full scale differential analog output level is specified in the analog characteristics specification table. mutec1 mutec2 mutec3 mutec4 mutec5 mutec6 41 26 25 24 23 22 mute control ( output ) - the mute control pins go high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. these pins are intended to be used as a control for external mute circuits on the line outputs to prevent the clicks and pops that can occur in any single supply system. use of mute control is not man- datory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. stand alone definitions m0 m1 m2 m3 17 16 15 42 mode selection ( input ) - determines the operational mode of the device as detailed in tables 6and7. control port definitions scl/cclk 15 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interface voltage in i 2 c mode as shown in the typical connection diagram. sda/cdin 16 serial control port data ( input/output )-sdaisadatai/olineini 2 c mode and is open drain, requiring an external pull-up resistor to the logic interface voltage, as shown in the typical con- nection diagram; cdin is the input data line for the control port interface in spi mode. ad0/cs 17 address bit 0 (i 2 c) / control port chip select (spi) ( input ) - ad0 is a chip address pin in i 2 c mode; cs is the chip select signal for spi mode. dsd definitions dsda1 dsdb1 dsda2 dsdb2 dsda3 dsdb3 3 2 1 48 47 46 direct stream digital input ( input) - input for direct stream digital serial audio data. dsd_sclk 42 dsd serial clock (input) - serial clock for the direct stream digital serial audio interface. dsd_en 7 dsd enable (input) - when held at logic ? 1 ? the device will enter dsd mode (stand-alone mode only). pin name # pin description
CS4362 26 *note: these modes are only available in control port mode by setting the mclkdiv bit = 1. mode (sample-rate range) sample rate (khz) mclk (mhz) control port only modes mclk ratio 256x 384x 512x 768x 1024x* single speed (4 to 50 khz) 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 mclk ratio 128x 192x 256x 384x 512x* double speed (50 to 100 khz) 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 mclk ratio 64x 96x 128x 192x 256x* quad speed (100 to 200 khz) 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 5. common clock frequencies m1 (dif1) m0 (dif0) description format figure 00 left justified, up to 24-bit data 033 01 i 2 s, up to 24-bit data 134 10 right justified, 16-bit data 235 11 right justified, 24-bit data 336 table 6. digital interface format, stand-alone mode options m3 m2 (dem) description 00 single-speed without de-emphasis (4 to 50 khz sample rates) 01 single-speed with 44.1khz de-emphasis; see figure 39 10 double-speed (50 to 100 khz sample rates) 11 quad-speed (100 to 200 khz sample rates) table 7. mode selection, stand-alone mode options dsd_mode (lrck1) m2 m1 m0 description 1000 64x oversampled dsd data with a 4x mclk to dsd data rate 1001 64x oversampled dsd data with a 6x mclk to dsd data rate 1010 64x oversampled dsd data with a 8x mclk to dsd data rate 1011 64x oversampled dsd data with a 12x mclk to dsd data rate 1100 128x oversampled dsd data with a 2x mclk to dsd data rate 1101 128x oversampled dsd data with a 3x mclk to dsd data rate 1110 128x oversampled dsd data with a 4x mclk to dsd data rate 1111 128x oversampled dsd data with a 6x mclk to dsd data rate table 8. direct stream digital (dsd), stand-alone mode options
CS4362 27 5. applications 5.1 grounding and power supply decoupling as with any high resolution converter, the CS4362 requires careful attention to power supply and grounding arrangements to optimize performance. figures 5 & 6 show the recommended power ar- rangement with va, vd, vls and vlc connected to clean supplies. decoupling capacitors should be located as close to the device package as possible. if desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin (see section 1 for rec- ommended voltages). 5.2 oversampling modes the CS4362 operates in one of three oversampling modes based on the input sample rate. mode selec- tion is determined by the m3 and m2 pins in stand- alone mode or the fm bits in control port mode. single-speed mode supports input sample rates up to 50 khz and uses a 128x oversampling ratio. double-speed mode supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode supports input sample rates up to 200 khz and uses an oversampling ratio of 32x. 5.3 recommended power-up sequence 1. hold rst low until the power supply, master, and left/right clocks are stable. in this state, the control port is reset to its default settings and vq will remain low. 2. bring rst high. the device will remain in a low power state with vq low and will initiate the stand-alone power-up sequence. the control port will be accessible at this time. if control port oper- ation is desired, write the cpen bit prior to the completion of the stand-alone power-up se- quence, approximately 512 lrck cycles in sin- gle-speed mode (1024 lrck cycles in double- speed mode, and 2048 lrck cycles in quad- speed mode). writing this bit will halt the stand- alone power-up sequence and initialize the control port to its default settings. the desired register set- tings can be loaded while keeping the pdn bit set to 1. 3. if control port mode is selected via the cpen bit, set the pdn bit to 0 which will initiate the pow- er-up sequence. 5.4 analog output and filtering the application note ?design notes for a 2-pole filter with differential input? discusses the sec- ond-order butterworth filter and differential to sin- gle-ended converter which was implemented on the CS4362 evaluation board, cdb4362, as seen in figure 42. the CS4362 does not include phase or amplitude compensation for an external filter. therefore, the dac system phase and amplitude response will be dependent on the external analog circuitry. 5.5 interpolation filter to accommodate the increasingly complex re- quirements of digital audio systems, the CS4362 incorporates selectable interpolation filters for each mode of operation. a ?fast? and a ?slow? roll-off filter is available in each of single, double, and quad speed modes. these filters have been de- signed to accommodate a variety of musical tastes and styles. the filt_sel bit is used to select which filter is used (see the control port section for more details). when in stand-alone mode, only the ?fast? roll-off filter is available. filter specifications can be found in section 1, and filter response plots can be found in figures 9 to 32.
CS4362 28 5.6 clock source selection the CS4362 has two serial clock and two left/right clock inputs. the sdinxclk bits in the control port allow the user to set which sclk/lrck pair is used to latch the data for each sdinx pin. the clocks applied to lrck1 and lrck2 must be de- rived from the same mclk and must be exact fre- quency multiples of each other as specified in the ?switching characteristics? on page 8. when using both sclk1/lrck1 and sclk2/lrck2, if ei- ther sclk/lrck pair loses synchronization then both sclk/lrck pairs will go through a retime period where the device is re-evaluating clock ra- tios. during the retime period all dac pairs are temporarily inactive, outputs are muted, and the mute control pins will go active according to the mutec bits. if unused, sclk2 and lrck2 should be tied static low and sdinx bits should all be set to sclk1/lrck1. in stand-alone mode all dac pairs use sclk1 and lrck1 for timing and sclk2/lrck2 should be tied to ground. 5.7 using dsd mode in stand-alone mode, dsd operation is selected by holding dsd_en(lrck1) high and applying the dsd data and clocks to the appropriate pins. the m2:0 pins set the expected dsd rate and mclk ratio. in control-port mode the fm bits set the device into dsd mode (dsd_en pin is not required to be held high). the dif register then controls the expected dsd rate and mclk ratio. during dsd operation, the pcm related pins should either be tied low or remain active with clocks (except lrck1 in stand-alone mode). when the dsd related pins are not being used they should either be tied static low, or remain active with clocks (except m3 in stand-alone mode). 6. control port interface the control port is used to load all the internal set- tings. the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference prob- lems, the control port pins should remain static if no operation is required. the CS4362 has map auto increment capability, enabled by the incr bit in the map register, which is the msb. if incr is 0, then the map will stay constant for successive writes. if incr is set to 1, then map will auto increment after each byte is written from register 01h to 08h and then from 09h and 11h, allowing block reads or writes of suc- cessive registers in two separate sections (the counter will not auto-increment to register 09h from register 08h). 6.1 enabling the control port on the CS4362 the control port pins are shared with stand-alone configuration pins. to enable the control port, the user must set the cpen bit. this is done by performing a i 2 c or spi write. once the control port is enabled, these pins are dedicated to control port functionality. to prevent audible artifacts the cpen bit (see sec- tion 3.1.1) should be set prior to the completion of the stand-alone power-up sequence, approximate- ly 1024 lrck cycles. writing this bit will halt the stand-alone power-up sequence and initialize the control port to its default settings. note, the cp_en bit can be set any time after rst goes high; how- ever, setting this bit after the stand-alone power- up sequence has completed can cause audible arti- facts. 6.2 format selection the control port has 2 formats: spi and i 2 c, with the CS4362 operating as a slave device. if i 2 c operation is desired, ad0/cs should be tied to vlc or gnd. if the CS4362 ever detects a high
CS4362 29 to low transition on ad0/cs after power-up and af- ter the control port is activated , spi format will be selected. 6.3 i 2 c format in i 2 c format, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with a clock to data relationship as shown in figure 7. the receiving device should send an ac- knowledge (ack) after each byte received. there is no cs pin. pin ad0 forms the partial chip ad- dress and should be tied to vlc or gnd as re- quired. the upper 6 bits of the 7 bit address field must be 001100. note: mclk is required during all i 2 c transac- tions. please see reference 4 for further details. 6.3.1 writing in i 2 c format to communicate with the CS4362, initiate a start condition of the bus. next, send the chip address. the eighth bit of the address byte is the r/w bit (low for a write). the next byte is the memory address pointer, map, which selects the register to be read or written. the map is then fol- lowed by the data to be written. to write multiple registers, continue providing a clock and data, waiting for the CS4362 to acknowledge between each byte. to end the transaction, send a stop condition. 6.3.2 reading in i 2 c format to communicate with the CS4362, initiate a start condition of the bus. next, send the chip address. the eighth bit of the address byte is the r/w bit (high for a read). the contents of the reg- ister pointed to by the map will be output after the chip address. to read multiple registers, continue providing a clock and issue an ack after each byte. to end the transaction, send a stop condi- tion. 6.4 spi format in spi format, cs is the CS4362 chip select signal, cclk is the control port bit clock, cdin is the in- put data line from the microcontroller and the chip address is 0011000. cs , cclk and cdin are all inputs and data is clocked in on the rising edge of cclk. note that the CS4362 is write-only when in spi format. 6.4.1 writing in spi figure 8 shows the operation of the control port in spi format. to write to a register, bring cs low. the first 7 bits on cdin form the chip address and must be 0011000. the eighth bit is a read/write in- dicator (r/w ), which must be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into register designated by the map. to write multiple registers, keep cs low and continue providing clocks on cclk. end the read transaction by setting cs high.
CS4362 30 6.5 memory address pointer (map) sda scl 001100 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 7. control port timing, i 2 cformat map msb lsb data byte 1 byte n r/w m ap = m em ory address pointer address chip cdin cclk cs 0011000 figure 8. control port timing, spi format 6.5.1 incr (auto map increment enable) default = ? 0 ? 0 - disabled 1-enabled note: when auto map increment is enabled, the register must be written it two separate blocks: from register 01h to 08h and then from 09h and 11h. the counter will not auto-increment to register 09h from register 08h 6.5.2 map4-0 (memory address pointer) default = ? 00000 ? 76543210 incr reserved reserved map4 map3 map2 map1 map0 00000000
CS4362 31 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 9. single speed (fast) stopband rejection figure 10. single speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 11. single speed (fast) transition band (detail) figure 12. single speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 13. single speed (slow) stopband rejection figure 14. single speed (slow) transition band
CS4362 32 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) figure 15. single speed (slow) transition band (detail) figure 16. single speed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 17. double speed (fast) stopband rejection figure 18. double speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 19. double speed (fast) transition band (detail) figure 20. double speed (fast) passband ripple
CS4362 33 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 21. double speed (slow) stopband rejection figure 22. double speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 23. double speed (slow) transition band (detail) figure 24. double speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 25. quad speed (fast) stopband rejection figure 26. quad speed (fast) transition band
CS4362 34 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 27. quad speed (fast) transition band (detail) figure 28. quad speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 29. quad speed (slow) stopband rejection figure 30. quad speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 31. quad speed (slow) transition band (detail) figure 32. quad speed (slow) passband ripple
CS4362 35 lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 33. format 0 - left justified up to 24-bit data lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb msb lsb lsb figure 34. format 1 - i 2 s up to 24-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks figure 35. format 2 - right justified 16-bit data lrck sclk left channel sdinx 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel figure 36. format 3 - right justified 24-bit data
CS4362 36 lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 figure 37. format 4 - right justified 20-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks figure 38. format 5 - right justified 18-bit data figure 39. de-emphasis curve gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz sdinx channel pair x control dac dac aoutax+ aoutax- aoutbx+ aoutbx- l r figure 40. channel pair routing diagram (x = channel pair 1, 2, or 3)
CS4362 37 ? a channel volume control aout ax aoutbx left channel audio data right channel audio data b channel volume control mute mute sdinx figure 41. atapi block diagram (x = channel pair 1, 2, or 3) figure 42. recommended output filter
CS4362 38 7. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10hz to 20khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/ c. 8. references 1. "how to achieve optimum performance from delta-sigma a/d & d/a converters" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2. cdb4362 evaluation board datasheet 3. ? design notes for a 2-pole filter with differential input ? by steven green. cirrus logic application note an48 4. ? the i 2 c-bus specification: version 2.0 ? philips semiconductors, december 1998. http://www.semiconductors.philips.com
CS4362 39 9. package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 48l lqfp package drawing e1 e d1 d 1 e l b a1 a

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